50 PIN ?? at the Computer.
Pin | Name | Dir | Description |
1 | /CS1 | OUT | Memory Read in addresses 4000-7FFF |
2 | /CS2 | OUT | Memory Read in addresses 8000-BFFF |
3 | /CS12 | OUT | Memory Read in addresses 4000-BFFF |
4 | /SLTSL | OUT | Low when Slot 2 (cartridge slot) is selected |
5 | n/c | - | Not connected. |
6 | /RFSH | OUT | Refresh signal from CPU |
7 | /WAIT | IN | OC, Tells CPU to wait. Refresh signal is not maintained |
8 | /INT | IN | OC, Requests a interrupt to CPU (call to addr 38h) |
9 | /M1 | OUT | CPU fetches first part of instruction from memory. |
10 | /BUSDIR | IN | NC, was used to control the data direction. |
11 | /IORQ | OUT | I/O request signal. (Address=Port) |
12 | /MREQ | OUT | Memory request signal. (Address=Address) |
13 | /WR | OUT | Write signal (strobe) |
14 | /RD | OUT | Read signal (strobe) |
15 | /RESET | IN | Reset |
16 | n/c | - | Not connected. |
17 | A0 | OUT | Address 0 |
18 | A1 | OUT | Address 1 |
19 | A2 | OUT | Address 2 |
20 | A3 | OUT | Address 3 |
21 | A4 | OUT | Address 4 |
22 | A5 | OUT | Address 5 |
23 | A6 | OUT | Address 6 |
24 | A7 | OUT | Address 7 |
25 | A8 | OUT | Address 8 |
26 | A9 | OUT | Address 9 |
27 | A10 | OUT | Address 10 |
28 | A11 | OUT | Address 11 |
29 | A12 | OUT | Address 12 |
30 | A13 | OUT | Address 13 |
31 | A14 | OUT | Address 14 |
32 | A15 | OUT | Address 15 |
33 | D0 | IN/OUT | Data 0 |
34 | D1 | IN/OUT | Data 1 |
35 | D2 | IN/OUT | Data 2 |
36 | D3 | IN/OUT | Data 3 |
37 | D4 | IN/OUT | Data 4 |
38 | D5 | IN/OUT | Data 5 |
39 | D6 | IN/OUT | Data 6 |
40 | D7 | IN/OUT | Data 7 |
41 | GND | ------ | Ground |
42 | CLOCK | OUT | CPU clock, 3.579 MHz |
43 | GND | ------ | Ground |
44 | SW1 | - | NC, Insert/remove detection for protection |
45 | +5V | OUT | +5 VDC (300mA max /slot) |
46 | SW2 | - | NC, Insert/remove detection for protection |
47 | +5V | OUT | +5 VDC (300mA max /slot) |
48 | +12V | OUT | +12 VDC (50mA max /slot) |
49 | SOUNDIN | IN | Sound input (-5dBm) |
50 | -12V | OUT | -12 VDC (50mA max /slot) |